Field of the Invention
The invention relates to a semiconductor memory cell configuration with dynamic memory cells, DRAMs for short, that in each case have a selection transistor and a memory capacitor. In the case of such a DRAM cell configuration, the information is stored in the memory cell in the form of electric charges, the memory states “0” and “1” respectively corresponding to a positively and negatively charged memory capacitor. The selection transistor and the memory capacitor of the memory cell are connected to one another in this case such that when the selection transistor is driven through a word line the charge of the capacitor can be read in and out through a bit line. The main outlay in the development of the technology of DRAM cell configurations lies in creating reliably operating DRAMs with a high packing density, that is to say, a low space requirement per memory cell. It is particularly important in this case that the memory capacitor has a memory capacity that ensures an adequate read signal and is, however, insensitive to α particles. To ensure satisfactory memory capacity even in the case of a small cell area, memory capacitors have been developed that use the third dimension. Such three-dimensional memory capacitors are configured chiefly in the form of trench capacitors that are produced such that there is etched into the semiconductor substrate a trench that is filled up with a dielectric layer and a first memory electrode, the semiconductor substrate serving as second memory electrode. The selection transistor of the DRAM cell is usually constructed on the planar semiconductor surface next to the trench capacitor. Such a cell configuration with a trench capacitor and a planar selection transistor requires at least a chip area of 8F2, F representing the minimum pattern size that can be produced by lithography with the technology in use. To be able to increase further the packing density of the DRAM cells, from generation to generation of memories the pattern size F has been reduced, on one hand, and the overall chip area has been enlarged, on the other hand. However, problems arise in the case of this DRAM development because of excessively low chip yield, extreme rises in costs being due to the downscaling of patterns in the chip production and ever-smaller ratios of capacitor capacitance to bit line length. For this reason, attempts are also being made in developing the technology of DRAMs to downscale the cell area of the DRAMs in order to be able to increase the packing density. One possibility for downscaling the cell size of the DRAM lies in this case of configuring the selection transistor in three dimensions in a way similar to the memory capacitor. Various DRAM cell concepts are already known in which a trench capacitor is connected to a selection transistor constructed substantially vertically as a MISFET. In the case of the known DRAM cell configurations with a vertical MISFET transistor and trench capacitor, there is the problem, however, that the active zone between the source electrode and the drain electrode is influenced by a word or bit line, adjacent to the DRAM cell, that is not used to control the relevant DRAM cell. This can lead, in particular, in the case of the small pattern sizes of the DRAMs, to a leakage current through the active zone of the MISFET and, thus, to a loss of information in the memory cell. To exclude influencing of the active zone of a vertical MISFET transistor, and thereby to prevent leakage currents, U.S. Pat. No. 5,519,236 to Ozaki proposes a semiconductor memory cell configuration in which the active zone between the source electrode and the drain electrode of the vertical selection transistor is completely surrounded by a gate structure. As a result, the active zone is shielded from adjacent word and/or bit lines. The known cell configuration is constructed in this case such that trenches and pillars are executed in a configuration with the pattern of a chessboard in the semiconductor substrate, the memory capacitor being executed in a trench, and the associated selection transistor being executed vertically in an adjacent pillar, and a gate electrode layer completely surrounding the active layer of the selection transistor. The gate electrode layer can, in this case, be part of a word line assigned to the DRAM. A bit line of the DRAM cell is, furthermore, disposed such that it runs, in a fashion offset perpendicularly from the trench capacitor, over the column of the associated vertical selection transistor, and is connected to the source electrode thereof. The chessboard pattern used in Ozaki for configuring the DRAM cells has, however, a large space requirement such that the maximum packing density of the DRAM cells on the semiconductor substrate remains limited. Furthermore, in the case of the design of the DRAM cell in accordance with Ozaki, it is necessary for the purpose of patterning the word line to carry out a plurality of complicated lithography steps with mask processes that, in turn, necessitate a specific minimum cell size and, thereby, greatly limit the maximum packing density of the DRAM cell configuration.
International Application WO 00/33383, corresponding to United States Patent Pub. 2002/017,671 A1 to Goebel et al., exhibits a classic configuration of memory cells with vertical transistors, in the case of which the active regions are surrounded by the electrodes of the source regions and drain regions and not by the layers forming the word lines whereas, in a way similar to Ozaki, the configuration has a distribution of the trench capacitors in the form of a chessboard pattern. Memory cell configurations of the type with a chessboard pattern and with trench capacitors are also described in Japanese Patent Document 05-291528 to Matsuo et al. Configurations, in the form of a chessboard, of vertical transistors for driving capacitors are exhibited in U.S. Pat. No. 4,937,641 to Sunami et al. and U.S. Pat. No. 4,967,247 to Kaga et al.